A printed wiring substrate, on which an integrated circuit pattern is formed by using a mask technology is employed in a motherboard of an electronic device or the like. A mask technology is disclosed in Japanese Laid-open Patent Publication No. 09-218032, for example.
Warpage is sometimes produced in a printed wiring substrate in accordance with a temperature condition of a reflow process for mounting an electronic part (an LSI (Large Scale Integration), for example) on the printed wiring substrate. The occurrence of such warpage causes non-adhesion or short-circuit of a bump join portion or the like of the electronic part, whereby the product yield is reduced.
Therefore, arts in which a CAD (Computer Aided Design) system and a finite element method are combined to structurally analyze a printed wiring substrate and predict warpage that is produced in the printed wiring substrate have been devised (see, for example, Japanese Laid-open Patent Publication No. 2004-13437, Japanese Patent No. 3329667, and Japanese Laid-open Patent Publication No. 2000-231579). With the related arts, as a result of the prediction, design modifications can be implemented to produce a printed wiring substrate with less warpage produced in the mounting process.
However, even with the related arts, predictions cannot be made with sufficiently high accuracy, thus warpage produced in the mounting process cannot be sufficiently suppressed.
Another related art is disclosed in Japanese Laid-open Patent Publication No. 2006-209629, which accomplishes the intended purpose. However, it is difficult to sufficiently suppress warpage produced in the mounting process.